In synchronous integrated circuits, the integrated circuit may be clocked by an external clock signal and perform operations at predetermined times relative to the rising and falling edges of the applied clock signal. Examples of synchronous integrated circuits include synchronous memory devices such as synchronous dynamic random access memories (“SDRAMs”), synchronous static random access memories (“SSRAMs”), and packetized memories like SLDRAMs and RDRAMs, and include other types of integrated circuits as well, such as microprocessors. The timing of signals external to a synchronous memory device may be determined by the external clock signal, and operations within the memory device are typically synchronized to external operations. For example, data output may be placed on a data bus of the memory device in synchronism with the external clock signal, and the memory device may output data at the proper times. To output data at proper timings, an internal clock signal may be developed in response to the external clock signal, and is typically applied to latches contained in the memory device to clock data. The internal clock signal and external clock must be synchronized to ensure the internal clock signal clocks the latches at the proper times to successfully capture the commands. In the present description, “external” refers to signals and operations outside of the memory device, and “internal” refers to signals and operations within the memory device. Moreover, although examples in the present description are directed to synchronous memory devices, the principles described herein are equally applicable to other types of synchronous integrated circuits.
To synchronize external and internal clock signals in modern synchronous memory devices, a number of different approaches have been considered and utilized, including delay locked loops (“DLLs”), as will be appreciated by those skilled in the art. As used herein, the term synchronized includes signals that are coincident and signals that have a desired delay relative to one another. FIG. 1 is a schematic illustration of a conventional DLL circuit 100 for providing an approximate delay that closely matches the phase difference between input and output clock signals. The DLL circuit 100 uses a feedback configuration that operates to feed back a phase difference-related signal to control one or more delay lines, such as a variable delay line 112, for advancing or delaying the timing of one clock signal to “lock” to a second clock signal.
An external clock signal is initially applied to the DLL circuit 100 and received by an input buffer 104 that provides a buffered clock signal DLY_REF to the DLL circuit 100. The DLY_REF signal is delayed relative to the external clock signal due to a propagation delay of the input buffer 104. The DLY_REF signal is then applied to variable delay line 112, which include a number of delay stages that are selected by a shift register 120 to apply a measured delay for adjusting the phase of the DLY_REF signal. The shift register 120 controls adjustments to the variable delay line 112 by providing shift control signals 134 in response to receiving control signals from a phase detector 130. In response to the shift control signals 134, the variable delay line 112 applies a measured delay to adjust the phase of the DLY_REF signal near the desired phase for achieving the phase lock condition. The variable delay line 112 generates an output signal CLK_OUT, whose phase is compared to the DLY_REF signal to determine whether the locking condition has been achieved. The CLK_OUT signal is provided to a model delay circuit 140 that duplicates inherent delays added to the applied external clock signal as it propagates through the delay loop, such as the input buffer 104 plus output path delay that may occur after the DLL. The model delay circuit 140 then provides a feedback signal DLY_FB to the phase detector 130. The phase detector 130 compares the phases of the DLY_REF signal and the DLY_FB signal to generate shift selection signals 132 to the shift register 120 to control the variable delay line 112. The shift selection signal instructs the shift register 120 to increase the delay of the variable delay line 112 when the DLY_FB signal leads the DLY_REF signal, or decrease the delay in the opposite case. The delay may be increased or decreased by adding or subtracting a number of stages used in the variable delay line 112, where the variable delay line 112 includes a number of delay stages. In this manner, the DLL 100 may synchronize an internal clock signal CLK_OUT with an external clock signal.
As was described above, the DLL 100 may take a certain amount of time to achieve a “locked” condition. This time may be shortened if the variable delay line 112 was initially set to a delay which approximates the anticipated needed delay to synchronize the internal and external clock signals. Minimal delay may be preferable for locking purposes due to lower power being consumed. In order to provide this initial delay, some DLL circuits may include a measurement initialization capability. FIG. 2 is a schematic illustration of a portion of a DLL including circuitry for measurement initialization. To highlight the measurement initialization circuitry, not all of the DLL circuitry (such as the phase detector) is shown in FIG. 2.
An external clock signal is provided to an input buffer 201 to generate a ref_clk signal. The ref_clk signal is provided to an input of a multiplexer 203. The multiplexer 203 may select an input corresponding to a control signal MUX received from a controller 210. Initially, the multiplexer 203 may be configured to allow the ref_clk signal to be provided to the variable delay line 205. The variable delay line 205 may be initially set to provide a minimal delay, that is set to minimize the tDLL time shown in FIG. 2, such that minimal delay stages may be used. The variable delay line 205 may be set in this manner responsive to a control signal vdl_cntrl from the controller 210. After the ref_clk signal passes through the variable delay line 205, it is provided to a model delay 212. The model delay 212 may generally model delays outside of the delay loop, such as delays from input buffers, etc. The model delay 212 then provides a signal to a tAC trim block 214. The tAC trim block 214 may generally compensate for access time delays as specified by a particular system. The tAC trim block 214 may then provide a signal to a latch 216, converting the received signal to signal (e.g. an edge or pulse) a ‘Start’ signal. The ‘Start’ signal may be provided to a buffer 218 which may then provide the signal to a second input of the multiplexer 203. The multiplexer may be controlled to then provide the ‘Start’ signal to the variable delay line 205. In this manner, a ‘Start’ signal begins propagating through the variable delay line 205.
The ref_clk signal may also be provided directly to the tAC trim block 214. The tAC trim block 214 may then provide the delayed signal to a latch 220, which may convert the ref_clk signal to a signal, referred to as a ‘Stop’ signal (e.g. edge or pulse). The ‘Stop’ signal may be provided to a buffer 222 and then provided to latches in the stages of the variable delay line 205. In this manner, the ‘Stop’ signal may stop (e.g. latch) the ‘Start’ signal as it propagates through the variable delay line 205. Information regarding the number of stages the ‘Start’ signal propagated through before receipt of the ‘Stop’ signal may be provided by the variable delay line 205 in the form of a vdl_meas signal indicating the stage at which the ‘Start’ signal was latched. The controller 210 may accordingly set the variable delay line 205 to use that number of stages through the vdl_cntl signal. In this manner, the variable delay line 205 may be initialized to a particular number of stages.
During normal operation, the multiplexer 203 is configured to select the ref_clk input to provide to the variable delay line 205. The output of the variable delay line 205 may be provided to an output buffer 225 to generate a synchronized output signal. Although not shown in FIG. 2, recall a phase detector may be used to compare the phase of the ref_clk signal and the clk_fb signal and adjust the delay of the variable delay line 205 during operation. Following lock, a delay between the external clock signal and the synchronized output signal may be N*tCK.
FIG. 3 is a schematic illustration of another portion of a DLL including circuitry for implementing the measurement initialization scheme shown in FIG. 2. A flip-flop 302 may receive a high signal (e.g. a logic ‘1’, which may be VCC) at its D input and a reference clock signal ref_clk at its clock input. The flip-flop 302 may provide a signal to the serial buffers 304 and 306, modeling delay, as with the model delay 212 of FIG. 2. The output of the buffer 306 may be considered the ‘Start’ signal and provided to a variable delay line 310. The ‘Start’ signal from the output of the buffer 306 may also be provided to the D input of a flip-flop 312. The ref_clk signal may also be applied to the clock input of the flip-flop 312. In this manner, the flip-flop 312 may provide a ‘Stop’ signal at the next rising edge of the ref_clk signal following the receipt of the ‘Start’ signal. The ‘Stop’ signal may be provided to the delay line 310 to latch the propagating ‘Start’ signal.